1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device in which a through hole to open a hole on the upper surface of interconnection and the side part thereof is formed.
2. Related Art
A method for manufacturing a semiconductor device with a multi-layer interconnection structure in which a conventional Al interconnection is used in reference to FIGS. 11 and 12. It is to be noted that FIGS. 11 and 12 are sectional process charts showing a conventional method for manufacturing a semiconductor device.
First, a lower layer interconnection 601 is formed on an insulating film 600 of a semiconductor substrate as shown in FIG. 11(a). Next, a through hole 603 is opened by photography or etching method after a layer insulating film 602 is formed on the whole surface of the lower layer interconnection 601 and flattened by CMP (Chemical Mechanical Polishing) method as shown in FIG. 11(b).
Further, a tungsten film (hereafter, referred to as W film) 605 is formed to fill in the through hole by, e.g., CVD (Chemical Vapour Deposition) method after an adherent layer 604 composed mainly of titanium nitride (hereafter, referred to as TiN) and titanium (hereafter, referred to as Ti) is formed by spattering or CVD method as shown in FIG. 11(c).
And then the metal layer (W film) 605 and the adherent layer 604 which cover other than inside of the through hole are removed by CMP method or by etching back as shown in FIG. 12(a). Finally, an upper layer interconnection 606 is formed as shown in FIG. 12(b).
As described above, since a conventional lower layer interconnection is usually large enough to cover all the through holes, the through hole can be formed on the upper surface of the lower layer interconnection without exception.
However, with the recent progress in making a design rule detailed, it has become difficult to form a lower layer interconnection large enough to cover all the through holes. For this reason, it has become necessary to form the through hole not only on the upper surface of the lower layer interconnection but also at the sidewall of a interconnection. For example, the through hole is formed at the end part of an extremely fine interconnection as shown in FIG. 13.
In the conventional interconnection structure, it was observed that the larger the amount of over-etching becomes in opening a through hole the higher the resistance at the through hole becomes as shown in FIG. 14. However, since the opening area of the lower layer interconnection does not usually become small even if the amount of over-etching is increased, it is impossible for the resistance at the through hole to rise.
The inventors have recognized that the above phenomenon has been caused by the sidewall of the lower layer interconnection was exposed on a plasma gas during the over-etching with the through hole formed on the sidewall of the lower layer interconnection. Considering this fact, we can understand that the resistance at the through hole rises with the following reason. Non-conductive reaction product (for example, fine particle such as aluminum fluoride and aluminum nitride) is formed as a material exposed on the sidewall of the lower layer interconnection (for example, an aluminum-based material) reacts with an etching gas (for example, fluorine-based gas and nitride-based gas), and the reaction product accumulates on the lower layer interconnection with, for example, an etching gas convection.
We can also understand that the interfacial resistance with the aluminum-based material rises since carbon-based gas or nitride-based gas is generated as the etching gas reacts at the sidewall of the exposed interconnection and the grain boundary at a titanium nitride film (hereafter, referred to as TiN film) at the bottom of the through hole is spread.
By the way, there is a need to achieve the over-etching at more than several hundreds of nanometers to obtain a good electrical conduction between all the interconnection patterns and through holes since the layer insulating film flattened by CMP method does not have a uniform thickness due to the density difference of interconnection pattern. For this reason, the amount of over-etching becomes excessive at a shallow through hole formed on a thin layer insulating film, and the resistance becomes high.
As described above, a method for forming a through hole without reacting the etching gas at the sidewall of the interconnection is desired.
Therefore, the object of the present invention is to provide novel and improved method for manufacturing a semiconductor device capable of forming a fine interconnection structure without making the resistance at the through hole high.